Testing of a new type SEU-tolerant SRAM

Abstract In high-energy physics experiments, it is a trend to implement digitalization in the front end of readout electronics based on Application Specific Integrated Circuits (ASICs), which are exposed radiation environment. As an important part ASIC, SRAM (Static Random-Access Memory) impressionable Single Event Upset (SEU) due Therefore, new SEU-tolerant cell structure was designed our previous work. this paper, test system for evaluating tolerance effect described, and chip’s performance environment presented. The results show that upset cross-section reduced by five times compared with ordinary 6T without increasing power consumption.